Static power dissipation is quickly becoming the main component to the overall power consumption of the modern microprocessor or integrated circuit (IC). As we reduce horizontal feature size of the transistors we also reduce the vertical feature size. Transistors are built by the vertical layering of electrically dissimilar materials with extremely low and precise geometrical tolerances at the atomic scale. Some of the vertical slices are significantly thinner than the horizontal features. The gate oxide layer which separates charge between the gate from the p and n channels of the substrate can be measured by counting atoms of thickness. As this vertical scaling continues beyond 32 nm, the electric polarization field will continue to weaken and thus the gate oxide loses the ability to separate charge. Because of this, electrons have a less restricted flow. This results in increased static power or “leakage power,” which is now becoming the dominant power loss as process technology continues to scale. Functional units (FUs) within a pipeline's execution stages account for a large percentage of the microprocessors “on chip” real-estate. The amount of leakage within a given process technology is largely proportional to the number of transistors on the die. As static leakage power dissipation continues to worsen as CMOS scaling continues, technologies that reduce or eliminate leakage power dissipation will be of paramount importance.
From an architectural perspective, the needs of each program running on a general purpose microprocessor are very different, as such high end microprocessors are usually designed to accommodate a broad range of different programs and applications. In many cases this results in an over design which may come in the form of an aggressive superscalar architecture that may have a large number of FUs. These FUs may be in the idle state for a significant amount of the time where they are incurring static leakage power without the benefit of doing real work.
Most modern microprocessors are equipped with performance monitoring capabilities to provide designers and programmers insight into the performance of a microprocessor during the execution of a process or program. These performance monitoring units can record “event” data for various types of performance events such as the utilization levels of pipelines execution units.